1. Field of the Invention
The present invention relates to a semiconductor device provided with a dummy pattern for alleviating irregularity of the surface due to an uneven density of a pattern being manufactured, and a method of placing such a dummy pattern.
2. Description of the Background Art
Conventionally, a semiconductor device has been known in which a dummy pattern is placed in an element isolating region so as to alleviate a problem of uneven or irregular surface of a separative insulating film, that is created in the element isolating region in chemical mechanical polishing (CMP) process due to sparseness of an originally designed element forming region pattern.
An example of dummy pattern being formed in an interconnection layer is disclosed in Japanese Patent Laying-Open No. 8-213396. An example of dummy pattern being formed with shallow trench isolation (STI) to separate element forming region patterns is disclosed in Japanese Patent Laying-Open No. 9-181159.
In recent semiconductor devices, STI has been utilized to separate all the elements therein, for simplification of manufacturing process. Thus, the element isolating region 103 as shown in FIG. 18 has become extremely large.
Referring to FIG. 18, trenches 103a, 103b are formed in element isolating region 103 of a semiconductor substrate 101, and an insulating film 102 is deposited to cover trenches 103a, 103b. Thereafter, CMP, etchback or the like is performed for planarization.
At this time, as shown in FIG. 19, a relatively large valley or depression is created on the surface of a separative insulating film 102a formed in the wide trench 103a as compared to the case of a separative insulating film 102b formed in the narrow trench 103b. 
A technique to prevent creation of such a large depression is to form, as shown in FIG. 20, a dummy pattern 105 in the wide trench 103a before deposition of insulating film 102, CMP or the like.
According to this technique, as shown in FIG. 21, the depression of the surface of separative insulating film 102a left within the wide trench 103a after CMP or the like becomes less obvious. Thus, compared to the case where CMP or the like was performed without provision of dummy pattern 105 as in FIG. 15, it is possible to improve evenness or flatness of the surface of separative insulating film 102a formed within the wide trench 103a. Consequently, greater planarization of the semiconductor device is achieved.
To further improve planarization or dimension control of the semiconductor device, it is effective to reduce a pitch (width) of dummy pattern 105. This enables dummy patterns 105 to be placed thoroughly over the entire semiconductor device, so that the planarization of the semiconductor device as well as the dimension control will further improve.
The conventional dummy patterns 105, however, were placed automatically by calculation automatic design (CAD) process, and they had a fixed pitch. It was difficult to place such dummy patterns 105 with a fixed, small pitch thoroughly over the entire semiconductor device, because not only the CAD processing time but also the CAD processing capacity required would increase, and the processing itself might become impossible.
Placing the dummy patterns 105 uniformly over the entire semiconductor device poses another problem that dummy pattern 105 would be placed even in a region where the pattern density is originally large. In such a case, sufficient improvement in planarization cannot be expected.
The present invention is directed to solve the above-described problem. An object of the present invention is to improve the planarization of a semiconductor device, and, at the same time, to reduce the CAD processing time and capacity required for placement of dummy patterns.
The semiconductor device according to a first aspect of the present invention includes: an element pattern formed on a semiconductor substrate; a first dummy pattern placed in the same layer as the element pattern; and a second dummy pattern placed in the same layer as the element pattern and having a pitch different from that of the first dummy pattern. Herein, patterns in the xe2x80x9csame layerxe2x80x9d refer to layers or portions that exist in or on the semiconductor substrate approximately at the same height, like, e.g., neighboring dummy patterns 5a and 5b shown in FIG. 13. The xe2x80x9celement patternxe2x80x9d refers to a pattern constituting an element, which is a concept including an active area pattern, an interconnection pattern and the like, as will be described later in detail.
By providing the first and second dummy patterns having different pitches from each other, it is possible, e.g., to place the first dummy pattern having a relatively large pitch in a wide region of an element isolating region, and to place the second dummy pattern having a relatively small pitch in a relatively small region. Thus, the dummy patterns can be placed thoroughly over the entire semiconductor device In addition, by placing the first and second dummy patterns according to pitch size, in descending order, for example, it is possible to substantially reduce a processing region for placement of the dummy pattern having the smaller pitch. As a result, compared to the case where dummy patterns with a fixed, small pitch are placed all over the regions, both the CAD processing time and the CAD processing capacity required can be reduced.
The element pattern may include an element forming region pattern (active area pattern) formed in the semiconductor substrate and isolated by an element isolating region. In this case, the first and second dummy patterns are placed in the element isolating region.
The element pattern may include an interconnection pattern formed on the semiconductor substrate. In this case, the first and second dummy patterns are placed around the interconnection pattern.
In either case, it is possible to place the dummy patterns thoroughly over the entire semiconductor device.
The semiconductor device according to a second aspect of the present invention includes: a plurality of mesh regions (divided regions) on a semiconductor substrate; an element pattern located within the mesh region; and a dummy pattern placed within the mesh region to occupy a certain ratio of an area therein determined according to an occupy ratio of the element pattern that is defined as a ratio of an area of the element pattern in the mesh region with respect to a total area of the mesh region.
Thus, by dividing the region on the semiconductor substrate into a plurality of mesh regions, and by placing the dummy pattern in each mesh region according to the occupy ratio of the element pattern therein, it becomes possible to appropriately place the dummy pattern in each mesh region according to the density of the element pattern therein. Thus, the dummy pattern can be placed thoroughly over the entire semiconductor device, and variation in degrees of irregularity among the mesh regions can be reduced. As a result, it is possible to improve the planarization of the semiconductor device. Further, by placing the dummy pattern of an appropriate size according to the density of the element pattern, the CAD processing time as well as the CAD processing capacity required can be reduced.
Preferably, the dummy pattern includes first and second dummy patterns having pitches different from each other. This helps further improve the planarization of the semiconductor device.
In either aspect, placement of the first dummy pattern and placement of the second dummy pattern are preferably carried out in different steps. In addition, if the semiconductor device has a first region in which the first dummy pattern is to be placed and a second region in which the second dummy pattern is to be placed, placement of the first dummy pattern in the first region and placement of the second dummy pattern in the second region are preferably carried out in separate steps. Further, it is preferable that the dummy patterns are placed according to pitch size, in descending order.
Thus, by placing the dummy patterns having different pitches in different steps, it is possible to reduce the CAD processing time and capacity.
The dummy pattern placing method according to the first aspect of the present invention is employed in a semiconductor device provided with a first dummy pattern with a relatively large pitch and a second dummy pattern with a relatively small pitch placed in the same layer. In this method, placement of the first dummy pattern and placement of the second dummy pattern are carried out in different steps.
This reduces the CAD processing time as well as the CAD processing capacity required, as described above.
The first and second dummy patterns may be placed in an element isolating region of the semiconductor device that is divided into a first region in which the first dummy pattern is to be placed and a second region in which the second dummy pattern is to be placed. In this case, the second dummy pattern is preferably placed in the second region after the first dummy pattern is placed in the first region.
Alternatively, the first and second dummy patterns may be placed around an interconnection pattern of the semiconductor device. The region between the interconnection patterns is divided into a first region in which the first dummy pattern is to be placed and a second region in which the second dummy pattern is to be placed. In this case, the second dummy pattern is preferably placed in the second region after the first dummy pattern is placed in the first region.
Thus, by distinguishing the regions for forming the first and second dummy patterns therein, it is possible to process the second region only at the time of placement of the second dummy pattern. Thus, the region for CAD processing is reduced, which can further reduce the CAD processing time and capacity.
The first dummy pattern may include a first upper dummy pattern and a first lower dummy pattern. The second dummy pattern may include a second upper dummy pattern and a second lower dummy pattern. In this case, data for placement of the first and second lower dummy patterns can be appropriated to data for placement of the first and second upper dummy patterns.
Such utilization of the data for placement of the lower dummy patterns as the data for placement of the upper dummy patterns can contribute to a further reduction in time and capacity of the CAD processing.
The dummy pattern placing method according to the second aspect of the present invention includes the following steps. A semiconductor chip region is divided into a plurality of mesh regions. A second occupy ratio that is defined as a ratio of an area of a dummy pattern to be placed in the mesh region with respect to a total area of the mesh region is determined based on a first occupy ratio that is defined as a ratio of an area of an element pattern located in the mesh region with respect to the total area of the mesh region. The dummy pattern is then placed within the mesh region to occupy an area satisfying the second occupy ratio.
Thus, by placing the dummy pattern within each mesh region based on the occupy ratio of the element pattern therein, it is possible to reduce variation in degrees of irregularity among the mesh regions. Thus, the planarization of the semiconductor device can be improved. In addition, by placing the dummy pattern of an appropriate size based on the first occupy ratio, it is possible to reduce both the CAD processing time and capacity.
The step of placing the dummy pattern includes the step of adjusting a size of the dummy pattern such that the dummy pattern occupies an area within the mesh region corresponding to the second occupy ratio. Thus, the size of the dummy pattern can be optimized, so that the CAD processing time and capacity required can be reduced.
The step of determining the second occupy ratio may include the step of, after determining the first occupy ratios in the respective mesh regions, performing Fourier transform to calculate occupy ratio distribution of the first occupy ratios over the entire semiconductor chip region. In this case, the step of placing the dummy pattern includes the step of placing the dummy pattern according to the occupy ratio distribution obtained.
Alternatively, the step of determining the second occupy ratio may include the step of, after determining the first occupy ratios in the respective mesh regions, calculating an average occupy ratio of the first occupy ratios of a plurality of mesh regions. In this case, the step of placing the dummy pattern includes the step of placing the dummy pattern according to the average occupy ratio obtained.
Thus, by calculating the second occupy ratio as described above, the dummy pattern can be selected and placed more efficiently.
It is preferable that the second occupy ratio is set smaller as the first occupy ratio is larger. Thus, it becomes possible to reduce variation in degrees of irregularity among the mesh regions.
The step of determining the second occupy ratio preferably includes the step of combining the first occupy ratio with an occupy ratio of element pattern in a corresponding lower layer to calculate the second occupy ratio. Herein, the xe2x80x9ccombiningxe2x80x9d means to determine the second occupy ratio by taking into consideration the first occupy ratio as well as the occupy ratio of element pattern in the lower layer. This includes not only the case where the occupy ratio of element pattern in the lower layer is simply added to the first occupy ratio, but also the case where the first occupy ratio is multiplied by a prescribed coefficient obtained from the occupy ratio of element pattern in the lower layer.
Thus, by determining the second occupy ratio even taking the irregularity in the lower layer into consideration, it becomes possible to alleviate the unevenness in the semiconductor device even if regions having dense patterns are stacked one on the other or regions having sparse patterns are stacked one on the other.
In either aspect, the first dummy pattern may be placed in a first cell region and the second dummy pattern may be placed in a second cell region, and the pitch of the first cell region may be made larger than the pitch of the second cell region. In this case, a ratio of an area of the second cell region being occupied by the second dummy pattern is made greater than a ratio of an area of the first cell region being occupied by the first dummy pattern.
Accordingly, it is possible to place the second dummy pattern in a small region where the first dummy pattern cannot be placed. This further reduces the variation in degrees of irregularity among the mesh regions.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.